1. Field of the Invention
The present invention relates to a digital phase locked loop system in which a phase locked loop is composed of digital circuit elements.
2. Description of the Prior Art
Various kinds of digital phase locked loop system have been developed recently. The digital phase locked loop system is a phase locked which loop is composed of digital circuit elements. In comparison with an analog system, imbalance due to components hardly used occurs, and there is an advantage to obtain the desired characteristics without any adjustment. On the contrary, in a digital phase locked loop system, generally the output of an oscillator is frequency-divided, and loop output can be obtained. Therefore, it is possible for a phase locked loop to be operated only with an input frequency, which is less one several decades of the maximum operation frequency of a logic circuit element to be used therefor.
In the case when the input frequency is higher than the clock frequency of a fixed oscillator, the ratio of frequency division must be made small, thereby causing the quantization to be rough and the loop characteristics to be bad. Especially, in a digital phase locked loop system for the input frequency which is several decades less than the maximum operation frequency in the logic circuit elements, it is difficult to adopt a complicated composition of circuits since influence due to the characteristics of logic circuit elements themselves, especially the delay characteristics, is large together with influences by errors in the quantization.
FIG. 1 shows one of the examples of a conventional phase locked loop system for input which is several decades (that is, 1/N when N is a positive integral number less than the frequency of an oscillator (OSC) 4.
The predetermined frequency which is generated by the oscillator 4, a clock pulse MCK, for example 75 MHz is frequency-divided at the ratio of frequency division predetermined by a frequency divider 7, and the output U is led out as phase locked loop clock signal PLLCK by a reversing circuit N1. The phase difference between the input signal PBSG and a phase locked loop clock signal PLLCK is detected as a computed value of the counter 1.
Clock pulse MCK which is the output of the oscillator 4 is shown in FIG. 2(1), the input signal PBSG is shown in FIG. 2(2), the phase locked loop clock signal PLLCK is shown in FIG. 2(3), and a signal QA which comes from the output terminal Q of a D-type flip-flop (DFF) 3 is shown in FIG. 2(4).
Clock pulse MCK, input signal PBSG and output signal QA of D-type flip-flop 3 are inputted into an AND gate G1. The output of the AND gate G1 is inputted into the clock input terminal CK of counter 1. The output signal CNTOUT of counter 1 is shown in FIG. 2(5).
The output signal U of frequency divider 7 inputted into the clock input terminal CK of the D-type flip-flop 8 and is simultaneously inputted to the clock input terminal CK of the D-type flip-flop 3 by a reversing circuit N1. Furthermore, the reversed output signal U is led out as phase locked loop clock signal PLLCK.
The output of AND gate G2 is inputted into the counter 1 and the register 5 as a reset signal RESET and is simultaneously inputted into the set terminal S of RS-type flip-flop 10. The reset signal RESET is shown in FIG. 2(6). In FIG. 2, a phase difference corresponding to the time from the UP timing (a) of the input signal PBSG to the UP timing (b) of the phase locked loop clock signal PLLCK occurs, and this timing can be measured by the counter 1 on the basis of the clock pulse MCK.
Namely, as the input signal PBSG, the output signal QA of the D-type flip-flop 3, in which the input signal PBSG are latched at the UP timing of the phase lock loop clock signal PLLCK, and the clock pulse MCK of the fixed oscillator 4 are inputted into the AND gate G1, the counter 1 into which the output of the AND gate G1 is inputted can calculate the timing (a) to (b). The counter 1 counts the pulse from the AND gate G1 until the reset signal RESET is inputted from another AND gate G2.
Both the output from the output terminal Q of D-type flip-flop 3 and the output from the output terminal Q of another D-type flip-flop 8 by which the former output is furthermore latched at the UP timing of the output signal U of the frequency divider 7 are inputted into the AND gate G2. At the UP timing of the reset signal RESET from the AND gate G2, the signal CNTOUT expressing the computed value of the counter 1 is latched by the register 5, and at the same time the counter 1 is reset in response to the reset signal RESET and is set at the start of the next input signal PBSG. Thus the next computing action is started.
A phase difference signal I outputted from the register 5 is shown in FIG. 2(7), and this signal I is inputted into the decoder 6 where it is decoded into signal E to express the corresponding ratio of frequency division. The signal E outputted from the decoder 6 is shown in FIG. 2(8) and is loaded into a frequency divider 7 as load signal G to express the ratio of frequency division by a data changeover switch 11.
Thus, according to the phase difference signal I between the input signal PBSG and the phase lock loop clock signal PLLCK, the clock pulse MCK of the oscillator 4 is frequency-divided to change the ratio of frequency division of a frequency divider 7 which emits the phase locked loop clock signal PLLCK, thereby causing the phases to coincide between the input signal PBSG and the phase locked loop clock signal PLLCK.
That is, the frequency divider 7 operates at the ratio "N" of frequency division when the phase of the input signal PBSG is coincident with the phase of the phase locked loop clock signal PLLCK, and the ratio of frequency division is set to such as N+1 or N-1 according to the degree of the phase difference, thereby causing the phases to be made coincident with each other.
The load signal G to express the ratio of frequency division, which is outputted from the data changeover switch 11 to the frequency divider 7 is loaded into the frequency divider 7 in response to the load clock signal F. This load clock signal F is emitted by the logic circuit 9 as shown in FIG. 2(9) when the output signal U of the frequency divider 7 becomes a specified value. The specified value N is 8 in FIG. 2, and the load signal G whose ratio of frequency division is [9] according to a data changeover switch 11 is outputted from the decoder 6 at the timing (c) since phase difference occurs between the timing (a) and (b), and the phase difference of the phase locked loop clock signal PLLCK is compensated to be zero at the timing (g).
Also, the load clock signal F is inputted to the frequency divider 7 and is simultaneously inputted into the reset terminal R of the RS-type flip-flop 10. Therefore, the RS-type flip-flop 10 is set by the output of the AND gate G2 and is reset by the load signal F from the logic circuit 9. The signal H from the output terminal Q of this RS-type flip-flop 10 is shown in FIG. 2(11) and is inputted into the data changeover switch 11.
The data changeover switch 11 inputs the output E which comes from the decoder 6, to the frequency divider 7 as load signal G when the signal H is a HIGH level and inputs a signal K to express a constant N, which has been defined in advance from a constant setting circuit 12, to the frequency divider 7 as load signal G when the signal H is a LOW level. For instance, in this example, the constant N is [8]. The load signal G to express the ratio of frequency division inputted into the frequency divider 7 from the data changeover switch 11 is shown in FIG. 2(10).
The phase difference between the UP timing (a) of the input signal PBSG and the UP timing (b) of the phase locked loop clock signal PLLCK is computed by inputting the clock pulse MCK from the oscillator 4 by way of the AND gate G1 in the counter 1. Then, the output signal CNTOUT is given to the register 5.
In the case when the output from an output terminal Q of the D-type flip-flop 3 is a HIGH level, i.e., the UP waveform of the output signal U of a frequency divider 7 is inputted in the D-type flip-flop 8, the UP waveform of the reset signal RESET can be obtained from the AND gate G2, thereby causing the output [3] of counter 1 to be stored in the register 5 and the phase difference signal I of the register 5 to be given to the decoder 6. Then the output E to express the previously corresponding ratio [9] of frequency division is outputted from the decoder 6.
The RS-type flip-flop 10 outputs the signal H of a HIGH level, in response to the reset signal RESET from the AND gate G2. Therefore, the data changeover switch 11 is changed over so that the output E from the decoder 6 can be inputted into the frequency divider 7 as load signal G, and according to the load clock signal F from the logic circuit 9 the load signal G, the output E is loaded into the frequency divider 7 at the timing (c) shown in FIG. 2(9). Thus, the frequency divider 7 operates at the ratio [9] of frequency division.
Also, the load clock signal F from the logic circuit 9 resets the RS-type flip-flop 10 at the DOWN timing (c), and the signal H from the output terminal Q is caused to be a LOW level. Thereby, the data changeover switch 11 outputs the signal K to express a constant N from the constant setting circuit 12 to the frequency divider 7 as load signal G. Therefore, even at the timing (d) and (e) when the load clock signal F of the logic circuit 9 is outputted after the timing (c), the signal K from the constant setting circuit 12 is loaded in the frequency divider 7, thereby causing the frequency dividing operation to be conducted at the frequency dividing ratio N=8.
Thus, after the reset signal RESET is outputted from the AND gate G2, the ratio [9] of frequency division to compensate a phase difference signal I to express the phase difference from the register 5 is loaded into the frequency divider 7 in the time up to the timing (c). Thereafter, the predetermined frequency dividing ratio N (=8) is loaded when the phase difference of signals PBSG and PLLCK is the per expected value [8], thereby the phase difference between the UP timing (f) of input signal PBSG and the UP timing (g) of phase locked loop clock signal PLLCK can become as small as possible.
In a phase locked loop system shown in FIG. 1, in order to prevent the phase lock loop signal PLICK from being compensated based upon the length of a pulse width when the pulse width of input signal PBSG has a digitally converted waveform and bad influence from affecting the characteristics of phase lock loop, the ratio of frequency division is compensated one or more defined number of times. Thereafter, the predetermined constant N is used as ratio of frequency division.
In the digital phase locked loop system shown in FIG. 1 as above mentioned, operation can be carried out at a response speed which is nearly equivalent to the limit of logic circuit elements. Thus even a simple composition can result in good characteristics.
However, in such a composition as shown in FIG. 1, the characteristics will become bad when the frequency of input signal PBSG is totally changed. For example, when the time axis of input signal PBSG which is a reproducing signal obtained from a magnetic tape is fluctuated accompanied with fluctuation of the traveling speed of a magnetic tape in a digital tape recorder, the lock of phase locked loop to reproduce a clock signal for reading signals from the reproducing signals may become unlocked. Actually, when the fluctuation becomes more than 2% to 3%, a phenomenon in which the lock is lost may occur.
In a digital phase locked loop system having such a composition as shown in FIG. 1, such a phenomenon in which lock is lost due to a cause of the fluctuation is explained with regard to FIG. 3.
Each waveform shown in FIG. 3(1) to FIG. 3(11) individually corresponds to each waveform in FIG. 2(1) to FIG. 2(11). A signal H outputted from the RS-type flip-flop 10 is shown in FIG. 3(11). While the signal H is a LOW level, the output K from the constant setting circuit 12 is always inputted into the frequency divider 7 as load signal G. In this case, for instance, N=8.
In FIG. 3, even though the phase difference between the UP timing (a1) of the input signal PBSG and the UP timing (b1) of the phase locked loop clock signal PLLCK is compensated at the timing (c1) of the load clock signal F (See FIG. 3(9)) from the logic circuit 9 as the frequency (or pulse width) of input signal PBSG becomes low (or long) after the UP timing (a1) show in FIG. 3(2), the ratio [8] of frequency division at the timing (d1) and (e1) thereafter is not coincident with the frequency (or pulse width) of the input signal PBSG. As a result, the difference may be accumulated at the UP timing (f1) of the phase locked loop clock signal PLLCK. Thereby such a problem in which the phase between the input signal PBSG and the phase locked loop clock signal PLLCK may greatly deviate occurs.